The invention relates to a method of manufacturing a semiconductor device having a semiconductor body comprising a surface-adjoining region substantially of a first conductivity type in which at least two insulated gate field effect transistors are provided, the source and drain zones of which are formed by surface-adjoining zones of a second conductivity type, in which in the region of the first conductivity type at least one further surface zone of the second conductivity type is formed which constitutes a conductive connection between one of the source and drain zones of one of said two field effect transistors and one of the source and drain zones of the other of said two field effect transistors, in which starting from the semiconductor body of which at least the surface-adjoining region is of p-type silicon, a doping mask is provided at the surface of the body, said mask having an aperture at the area of the surface zone to be provided, in which, at the area of the field effect transistors to be provided, layer portions are present of a material masking the body against oxidation, in which via the aperture in the doping mask atoms selected from the group As and Sb are provided in the semiconductor body, after which the body with thereon an oxidation mask comprising the layer portions is subjected to an oxidation treatment so as to obtain an oxide pattern which is at least partly sunk in the semiconductor body and which extends beside the layer portions masking against oxidation and above the surface zone, in which during the oxidation treatment the As or Sb atoms provided in the body at the area of the surface zone diffuse deeper in the semiconductor body below and adjoining the sunken oxide to form the n-type surface zone, after which at the area of the field effect transistors to be formed the insulated gate electrodes are provided which, viewed on the surface, are situated on either side of and laterally spaced from the surface zone, and the source and drain zones of the field effect transistors adjoining the sunken oxide pattern are provided in a self-registering manner by means of doping with an impurity selected from the group P, As and Sb down to a depth at which the zones of the field effect transistors to be connected together adjoin the surface zone present below the sunken oxide pattern.
Such a method is disclosed in U.S. Pat. No. 4,101,344. In addition to a conductor pattern which is separated from the semiconductor body by insulating material and which connects the circuit elements together and to external supply conductors, the manufactured semiconductor device has a number of doped zones provided in the semiconductor body, which zones also serve to connect circuit elements together. Such doped zones, sometimes termed underpasses, inter alia present the advantage that crossing connections can be realized in the circuit in a comparatively simple manner. The underpasses constitute an extra layer of connections separated from the layer(s) of the insulated conductor pattern, as a result of which the whole connection pattern can become simpler and/or contact apertures for connecting circuit elements to the connection pattern can be saved.
Notably in integrated circuits in which the dimensions of the circuit elements are comparatively small, the space which is required for the whole connection pattern is decisive to a considerable extent of the semiconductor surface area required for the integrated circuit. In such circuits the use of underpasses can be of great usefulness. This applies in particular when the underpasses need occupy little space (surface area) and no critical alignment operations or other critical treatments are necessary during the manufacture for providing the underpasses.
Accurate alignment steps are preferably avoided generally in semiconductor technology. Such steps usually are rather laborious. In addition, the possibility of errors in the ultimate semiconductor device increases considerably with the number of critical operations during the whole manufacturing process. Furthermore, critical alignment steps can impose limits on the smallest dimensions and hence on the packing density of the device to be manufactured. In the underpasses obtained according to the method described in U.S. Pat. No. 4,101,344, the dimension thereof in the direction proceeding from one field effect transistor to the other is not particularly critical. If the layer portions masking against oxidation also prevent the penetration of doping material, the doping aperture in said direction is self-registering. When this is not the case, in so far as the aperture in the doping mask overlaps the oxidation mask and said overlap is not too large, then the dopant provided in the overlapping part will ultimately be present in the electrode zones of the field effect transistors. In the other direction transverse to the first-mentioned direction, however, the dimension of the underpass is fixed by the doping mask, the fact having to be taken into account that the doping mask and the oxidation mask have to be aligned relative to each other.